The present application relates to semiconductor technology. More particularly, the present application relates to a semiconductor structure containing threshold voltage tuned vertically stacked silicon germanium alloy nanowires. The present application also provides a method of forming such a semiconductor structure.
The use of non-planar semiconductor devices such as, for example, FinFETs, trigate and gate-all around semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Such non-planar semiconductor devices can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Multiple threshold voltage options for non-planar devices are required to meet the wide variety of power-performance criteria required of microarchitectural circuit blocks. It is however difficult to obtain multiple threshold voltages in such non-planar devices due to the limited options such as, for example, using different work functional metals, which are available. In addition, device width quantization is more pronounced in stacked semiconductor nanowire devices which makes it difficult to select drive strength and threshold voltage together in a meaningful way.
In view of the above, there is a need for providing a multiple threshold voltage option for gate-all around stacked semiconductor nanowires which is capable of meeting the wide variety of power-performance criteria required of microarchitectural circuit blocks and which can circumvent the problem of width quantization.